3D integration is becoming increasingly important for realizing advanced electronic systems, be it for advanced server-based compute and AI systems, chiplet integrated edge AI, augmented reality systems, sensor-fusion computation, automotive advanced driver assistance processors or handheld devices. These applications require 3D-interconnects at different levels of the electronic system hierarchy, resulting in a very broad range of 3D interconnect density requirements, which are made possible by an increasingly sophisticated range of 3D Interconnect technologies, from package, interposer to die-to-die and wafer-to-wafer stacking technologies. In this presentation, we present imec’s vision on this 3D interconnect technology landscape and present an update on our advanced technology research roadmap in this area. We report fine pitch RDL integration with 500 nm line/space capability, die-to-wafer hybrid bonding down to 2 µm pad pitch and wafer-to-wafer bonding down to 400nm pad pitch.
