Backside power delivery: Game changer and key enabler of advanced logic scaling and new STCO opportunities

De-coupling signal and power wiring by using both wafer sides for routing such that the latter is moved to the wafer’s backside (BS) is an innovative and game changer approach for on-chip power delivery (PD). It enables improved routing efficiency with lower IR drop values, key for supporting the compute scaling roadmap. This concept was first experimentally demonstrated by imec using a scheme with buried power rails (BPR) connected from the BS via scaled nano-TSVs to BSM1. Data showed no p/n-devices impact from extreme wafer thinning, with the possibility to further improve their characteristics by using optimized post-BS anneal(s). Beyond that, other implementation options have also started to be explored in terms of higher cell scalability potential, and in anticipation of their co-integration with advanced device architectures, e.g., 3D stacked structures like CFET. In particular, a scenario where the transistor’s source (bottom device in CFET) is directly contacted from the BS is not only attractive from a scalability potential, but it can also allow new opportunities for device engineering, with stress, contact resistance, thermal (chip vs. transistor level; hotspots) aspects assessed for various configurations.

Moreover, BSPD has the potential to expand towards a more optimum use of both wafer sides by addition of other functions/specific devices after BS processing, with clear benefits already seen, e.g., for ESD diodes built with BS contacts and for clock distribution implemented with (partial) BS routing. This concept is thus paving the way towards a truly functional BS roadmap. That is key for enabling the vision of a future, more versatile CMOS heterogenous platform (CMOS 2.0) which, under the umbrella of system-technology-co-optimization (STCO), can allow enhanced system performance and be customized to meet the diverse needs of a continuously increasing wide range of applications.