Towards CMOS 2.0: A framework for cross-technology co-optimization

Grand Ballroom West - 3F
15:15 - 15:35

Abstract

To enable the continued scaling of future AI compute systems, the industry is increasingly turning to the heterogeneous integration of multiple technologies within high-density packages. In the vision of CMOS 2.0, this integration extends into the very foundation of the CMOS technology platform itself. However, advanced 3D assembly and backside technologies introduce significant challenges—particularly in power delivery and thermal management. These developments are driving a rethinking of the entire memory subsystem, encouraging the adoption of novel memory technologies, and prompting a reconsideration of data movement at the package level, potentially even requiring fundamental changes to compute architectures. To effectively chart a path forward, we must take a holistic approach—one that supports systematic benchmarking and technology pathfinding. In this presentation, we will outline imec’s strategy to address these challenges through its cross-technology co-optimization framework.