Speaker

Julien Ryckaert

VP R&D - imec

Biography

Julien Ryckaert received the M.Sc. degree in electrical engineering from the University of Brussels (ULB), Belgium, in 2000 and the PhD degree from the Vrije Universiteit Brussel (VUB) in 2007. He joined imec as a mixed-signal designer in 2000 specializing in RF transceivers, ultra-low power circuit techniques and analog-to-digital converters. In 2010, he joined the process technology division in charge of design enablement for 3DIC technology. Since 2013, he is in charge of imec’s design- technology co-optimization (DTCO) platform for advanced CMOS technology nodes. In 2018, he became program director focusing on scaling beyond the 3nm technology node as well as the 3D scaling extensions of CMOS. Today, he is vice president logic in charge of compute scaling.

Talk(s)

3:05 PM

Towards CMOS 2.0: A framework for cross-technology co-optimization

To enable the continued scaling of future AI compute systems, the industry is increasingly turning to the heterogeneous integration of multiple technologies within high-density packages. In the vision of CMOS 2.0, this integration extends into the very foundation of the CMOS technology platform itself. However, advanced 3D assembly and backside technologies introduce significant challenges—particularly in power delivery and thermal management. These developments are driving a rethinking of the entire memory subsystem, encouraging the adoption of novel memory technologies, and prompting a reconsideration of data movement at the package level, potentially even requiring fundamental changes to compute architectures. To effectively chart a path forward, we must take a holistic approach—one that supports systematic benchmarking and technology pathfinding. In this presentation, we will outline imec’s strategy to address these challenges through its cross-technology co-optimization framework.