Eric Beyne - imec (02:55-03:15pm)

Abstract: 2.5D ‘Chiplet’ and 3D-SOC integration: heterogeneous technology system scaling
As electronic systems become more complex and CMOS scaling becomes more specialized, the traditional monolithic single-chip system integration gives way to a multi-die heterogenous integration technology. Two main directions can be observed “chiplet” and the “3D-SOC” approach. The “chiplet” approach brings together die that are independently designed and fabricated but share a standardized interface protocol to realize the desired combined function. The “3D-SOC” approach builds upon the highly successful system-on-chip (SOC) design methodology but allows different parts of the system to be fabricated using different technologies, stacked in multiple layers but co-designed without the addition of additional interface circuitry. 

To realize 2.5D chiplets or 3D SOC, a broad range of interconnect technologies are required. This requires a hierarchical 3D-interconnect view, defining a 3D-interconnect technology landscape, which extends from the package level all the way to the transistor level, spanning eight orders of magnitude in 3D-interconnect density.  This landscape is highly dynamic, as each technology has its own roadmap and scaling roadmap. This presentation will cover imec’s vision and contributions to 3D-interconnect scaling.