Speaker

Martin van den Brink

Former President & CTO - ASML

Biography

Dutch national, 1957, Vice Chair of the Board of Management since 2013 (term expires in 2024). Martin joined ASML in 1984 as an engineer and was appointed to the Board of Management in 1999 as Executive Vice President Marketing & Technology.

Martin earned a degree in electrical engineering from HTS Arnhem (HAN University) and a degree in physics from the University of Twente in the Netherlands in 1984. That same year, he joined newly-founded ASML. 

- Imec Lifetime of Innovation Award (2019) 
- IEEE Robert N Noyce Medal for exceptional contributions to the microelectronics industry (2015) 
- IEEE Cledo Brunetti Award for contributions to nanotechnology (2014) 
- Knight of the Order of the Dutch Lion (Orde van de Nederlandse Leeuw, 2014) 
- Honorary doctorate in physics from the University of Amsterdam (2012) 
- SPIE Frits Zernike Award for Microlithography for outstanding accomplishments in the development of semiconductor lithographic imaging solutions (2008) 

Talk(s)

11:50 AM

Holistic lithography drives system energy efficient performance

Almost 60 years later, the lasting impact and benefits of Moore's Law continues, not just as a law of physics, predicting the shrink of feature sizes, but in fact as an empirical law of economics: The number of transistors per device will keep increasing at a certain rate, as long as the value outweighs the cost. 

With current AI trends driving demand for diverse applications, there are constraints such as energy consumption, computing power and massive data assembly challenges. To sustain this trajectory, a combination of leading-edge and mainstream semiconductor technologies is indispensable. 

This presentation will explore the evolution of Moore’s Law from the principle of transistor density increase to a paradigm of “System energy-efficient performance” improvements. Speed and energy efficiency gains will be realized by innovating on total system integration, which in turn will drive up the number of transistors per device for the foreseeable future.

The future lies in the development of advanced 3D stacked architectures, where interconnected chip(let)s enable greater transistor density without compromising electrostatic performance. Despite the inevitable slowdown in the rate of shrinkage due to physical limitations, the integration of 3D stacking promises to prolong the scalability of semiconductor devices. Complementing these advancements, ASML’s holistic lithography enhancements, encompassing productivity, resolution and EPE, play a pivotal role in streamlining process integration, thus facilitating cost-effective and energy-efficient shrinkage.

ASML's continuous drive for innovation will support this trend. ASML’s EPE roadmap, which is key to our holistic lithography portfolio, will be enabled by further improvements to lithography platforms and developments within our applications (including metrology and inspection) roadmap. This is further advanced by EUV lithography, a technology unique to ASML, now in high-volume production, allowing simpler, cost-effective production at the 5 nm node. The latest generation in EUV, the EXE, or ‘High NA EUV’ lithography will enable multiple future nodes, and will extend Moore’s Law into the next decade.