Powering the AI supercycle: AI driven design for the CMOS 2.0 era

Artificial intelligence is redefining semiconductor progress from the device level through full systems, driving a transition from traditional geometric scaling to system-level scaling enabled by heterogeneous integration. As the industry enters the CMOS 2.0 era—angstrom-scale devices, CFET architectures, and 3D-connected heterogeneous stacks—design complexity now spans electrical, thermal, power, and mechanical domains simultaneously, requiring cross-technology co-optimization (XTCO) as a first-class discipline. The convergence of design for AI—semiconductors and systems optimized for rapidly evolving AI workloads—and AI for design—AI-driven methods embedded across electronic design automation (EDA) and system design and analysis (SDA)—is the foundational platform for XTCO and the design of the next generation of AI and intelligent systems. By enabling holistic, system-driven exploration of the CMOS 2.0 design space, this approach provides a clear and scalable path forward—one that allows the industry to continue delivering performance, energy efficiency, and manufacturability leadership in an AI-defined future. As we navigate this transformative era, it is imperative for leaders in the semiconductor industry to embrace these methodologies. CMOS 2.0 will be driven by physics‑grounded AI that co‑optimizes every layer of the stack—turning multi‑domain complexity into a scalable engine for performance, energy efficiency, and manufacturability in an AI‑defined world.