Speaker

Yuh-Jier Mii

EVP & Co-COO - TSMC

Biography

Dr. Yuh-Jier Mii is EVP and Co-Chief Operating Officer at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). Dr. Mii joined TSMC in 1994 as a manager at Fab 3 and then joined the company's R&D organization in 2001. In 2011, Dr. Mii was appointed Vice President of Research and Development and later he was promoted to Senior Vice President in November 2016.

In more than two decades of services at TSMC, Dr. Mii has contributed greatly to the development and manufacturing of advanced CMOS technologies in both Fab Operations and R&D. He successfully managed the development of 90nm, 40nm and 28nm technologies. By spearheading the research and development of 16nm, 7nm, 5nm, 3nm, and beyond, he has helped maintain TSMC's technology leadership in the foundry segment of the global semiconductor industry.

Dr. Mii received the IEEE Frederik Philips Award in 2022, recognizing his outstanding accomplishments in the management of research and development. Before joining TSMC, Dr. Mii was a research staff member at IBM Research Center.

Dr. Mii has 34 patents globally, including 25 US patents, and holds a B.S. in electrical engineering from National Taiwan University, as well as an M.S. and Ph.D. in Electrical Engineering from the University of California, Los Angeles (UCLA).

Talk(s)

11:25 AM

Shaping a better world with semiconductor innovations

The semiconductor industry is powered by relentless innovations in materials, processes, devices, advanced packaging, circuit design, EDA, computing architecture, algorithms, and software. Technology scaling has been the key driving force behind the numerous innovations that have enabled and unleashed a vast spectrum of applications from artificial intelligence (AI), high-performance computing (HPC), wireless connectivity, autonomous driving, to consumer electronics. Technology scaling has also undergone significant changes over the past decades, a trend will continue into the future. At chip level, scaling continues to drive the power, performance, and area (PPA) of future products. Progression in lithography, device architecture, new materials, integration schemes, and design technology co-optimization (DTCO) will continue to drive new technology nodes. Looking into the future, new device architectures such as CFET and novel low-dimensional channel materials could provide significant scaling benefits. Beyond chip-level scaling innovations, advanced packaging technologies have become increasingly important to achieve system-level performance, integrating more compute resources, memory, and logic to address memory bandwidth, power delivery, and I/O bottlenecks. These advanced integration capabilities enhance data transfer rates, reduce latency, optimize power consumption, and elevate the overall performance of computing systems. Advanced technology scaling at both chip level and system level will continue to drive system performance to new heights for the foreseeable future.