3D Interconnects for bonding and packaging: alignment challenges and solutions

3D interconnects can be realized at different levels of the electronic interconnect hierarchy. For realizing high density 3D interconnects overlay and pitch bonding accuracy are key enablers both for memory and logic modules. While lithographic alignment strategies are well-established in semi-conductor manufacturing and these methodologies and tools play a crucial role in 3D interconnect fabrication, it is important to emphasize that the total overlay achieved is still different than the post bond overlay. There is a strong influence of module, material and process choices. To achieve high density 3D interconnects a wide range of technologies are required. Technology elements include high density wafer to wafer and die to wafer stacking, silicon and reconstructed wafer interposers, high performance heat spreading and cooling, high speed I/O connections, improved power delivery network, through silicon and through dielectric vertical connections. In this talk different scenarios will be illustrated for realizing future 3D interconnects.