Mark Kuemerle

Experienced Technical Leader with a proven track record of defining next generation semiconductor and optical solutions. Broad experience teaming throughout our industry to develop an ecosystem for chiplet based systems (OCP ODSA, HMC consortium, DPC Test Team), currently leading specification of open low power interface. Responsible for defining leading-edge ASIC offering, competitiveness and also architecting system level solutions on our ASIC platform. Driving novel, cost effective solutions to enable next generation Co-Packaged Optics. Highly skilled in ASIC architecture, memory and IO architecture, power and timing methodology, source synchronous interface architecture and implementations, next generation packaging and interconnect and optical integration.