Scaling AI systems beyond the chip: the rise of panel-level packaging

AI and HPC applications are driving the semiconductor industry toward an inflection point: the future will no longer be powered by transistor scaling alone, but by the ability to integrate entire systems with unprecedented interconnect density, bandwidth and efficiency. Larger, more complex packages are stretching conventional wafer-level approaches, making panel-level packaging essential for the scale and manufacturing efficiency next-generation systems will require. Before this can be realized at scale, however, significant challenges remain across panel-level design, material selection, reliability, integration, and panel-scale processing. This talk will explore the coming transition from chip scaling to system scaling, why panel-level packaging is poised to become a foundational capability for AI and HPC, and how imec-Spain is being established as a new engine for this transformation by advancing materials R&D that is needed to enable these future package architectures.