3D integration as key enabler of future compute and memory

Innovative 2.5D and 3D wafer level packaging technologies are key enablers of future electronic systems. High density 3D integration allows for increased functionality and performance optimized for high bandwidth at low energy and cost with minimal latency. Massively parallel, application specific compute hardware needs massive local memory storage and data communication bandwidth.

3D interconnects can be realized at different levels of an electronic system with an interconnect hierarchy all the way down to the standard cell level. The density needs drive fine pitch 3D connectivity using wafer-to-wafer, die-to-wafer hybrid bonding technologies, while a thermally efficient layer stack design through appropriate heat spreading and cooling solutions must be maintained and also allow for vertical power delivery. 3D plays an important role in several application domains already today. Looking into the future, the importance is only expected to increase, for example, by taking the path from multiple-chip modules towards future CMOS2.0 and vertical architectures.

The overall 3D System Integration activities at imec focus on exploring the feasibility of new concepts and integration schemes. These new concepts often drive new manufacturing steps, modules, whereby novel thermal and integration challenges arise as well. As a neutral R&D partner imec provides application context, unique vehicles, infrastructure, methods and fundamental understanding of mechanisms to allow for exploring beyond what foundries can do and derisk potential future technology options.