Enabling circuit design on imec Pilot Line: PDKs for advanced memory & interconnects

Whether you are building AI accelerators, exploring chiplet-based architectures, or working on HPC or edge systems, this presentation shows how you will be able to leverage the NanoIC pilot capabilities using Process Design Toolkits (PDKs).  Embedded DRAM (eDRAM), redistribution layers (RDL), and hybrid bonding (HB) are three key enablers of next-generation system performance developed on the NanoIC pilot line that will ultimately enable compact, high-bandwidth, and power-efficient integration strategies. Early access to these technologies will be provided to the design community using a maturing series of PDKs to support early design exploration, concept demonstration, and ultimately manufacturing. These toolkits are technical enablers but also bridges between design communities and the silicon capabilities, and facilitate engagement from academia, SMEs, and startups. They intend to lower the barriers to advanced heterogeneous integration and accelerate learning, innovation, and small volume production in Europe.