Capacitor-less embedded DRAM: a game-changer for memory scaling

Conventional memories such as SRAM and DRAM face severe scaling limits: DRAM requires a storage capacitor with complex integration, while SRAM relies on six transistors, resulting in a large bit cell footprint. A disruptive alternative is a capacitor‑less embedded DRAM concept based on a compact two‑transistor (2T0C) cell, addressing both challenges. Leveraging IGZO’s ultra low off current, long data retention is achieved using parasitic capacitance, enabling simplified BEOL compatible integration. The technology supports high performance on-chip embedded DRAM with retention from minutes to hours, fast operation, and excellent endurance. As part of Europe’s effort to reinforce technological leadership in memory via the NanoIC project, imec, Tyndall, LETI and CSSNT jointly advance this concept through denser 2T0C architectures and exploration of alternative channel materials.