Interposer: one substrate to connect them all

In current AI systems, interposers act as the "universal interface" for heterogeneous integration, enabling high-speed communication between logic dies (GPUs/ASICs) and High Bandwidth Memory (HBM). By utilizing Through-Silicon Vias (TSVs) and fine-pitch redistribution layers (RDL), interposers achieve interconnect densities tens to hundreds of times greater than traditional packaging, improving the communication bandwidth and reducing signal latency among the stacked dies. Within the NanoIC pilot line, imec is developing platform flows offering Si and polymer-based RDL interposer build-ups.

Si interposers benefit from established CMOS processing technology that can enable scaling of interconnect density. This provides a versatile interposer platform where additional functionality can be enabled such as voltage regulators, decoupling capacitors, interconnect repeaters, ESD protection, etc.

For polymer-based RDL interposers, recent advances in photo patternable materials and lithographic processing have significantly improved resolution and overlay performance. Improved overlay control between metal lines and vias directly supports tighter via patterning and higher interconnect density. As a result, the interconnect pitch of polymer-based RDL can now be scaled to levels comparable with silicon interposers. Combined with a dual-damascene integration scheme, the fine pitch polymer RDL interposer developed in the NanoIC line offers a cost-effective solution for high density interposer substrates.