3D Integration bonding roadmap

The demand for higher interconnect density in advanced stacked semiconductor devices and new architectures is driving the evolution of 3D integration bonding technologies. Key applications, such as CMOS Image Sensors, 3D NAND Flash Memory, and next-generation DRAM, are pushing the boundaries of interconnect scaling. At the same time, emerging innovations—including Backside Power Delivery Networks, Stacked CFET Transistor Designs, and the integration of new materials—require novel approaches to bonding and layer transfer.

Achieving these advancements at a cost-effective scale necessitates both precise alignment (On Product Overlay – OPO) and the reduction of stacked layer thickness to optimize performance and manufacturability. Controlling these factors is critical to meeting the increasing complexity of device integration while maintaining cost efficiency.

Aligned with IMEC’s vision for CMOS 2.0, our approach focuses on enabling the heterogeneous stacking of diverse functional layers to enhance power efficiency, performance, and miniaturization. We will present recent achievements, ongoing challenges, and the future roadmap for 3D integration bonding. We will explore technological enablers and process innovations that will shape the next generation of semiconductor devices. By addressing these key aspects, we aim to provide insights into the evolving landscape of 3D integration and its role in future semiconductor scaling.