Cassie Sheng

Dr. Sheng is a semiconductor researcher and Senior R&D Process Integration Engineer at imec, focusing on sub‑1 nm pathfinding and Monolithic CFET integration, including MOL modules and wafer‑backside‑contact schemes. She also leads integration activities for imec’s NSH maturity program, aiming to enable 14A technology maturity across key process modules in imec. She received her Ph.D. in Materials Science from Hanyang University, where she studied IGZO‑based oxide semiconductor transistors. Before joining imec, she worked in memory solution at Hisilicon, leading 2T0C DRAM integration in a 300 mm environment and contributing to HBM development with improvements in failure‑analysis methodology.