Launching Europe into the nanosheet era

As the semiconductor industry moves beyond conventional FinFET scaling, gate-all-around (GAA) nanosheet transistors are emerging as the critical device architecture for enhancing performance and power efficiency at the most advanced logic nodes. For Europe, establishing advanced logic capabilities is essential to maintaining technological leadership and reinforcing strategic autonomy. Accordingly, the development of a nanosheet transistor baseline has been identified as a key objective of the NanoIC pilot line. The talks present the end-to-end development flow enabling this objective. The effort begins with the establishment of robust unit process building blocks and creation of a repeatable nanosheet device baseline.  In parallel, pathfinding PDK enablement provides the abstraction necessary for early-stage design exploration. Together, these activities create low-barrier access to nanosheet technologies targeting 2 nm and beyond logic nodes. Equipment and materials suppliers will be able to evaluate and optimize next-generation tools and process solutions, while start-ups, universities, and industrial partners will gain access to research PDKs for system-level pathfinding and innovation. Through these capabilities, the initiative aims to strengthen the European semiconductor ecosystem and accelerate the exploration of future logic technologies beyond the 2 nm node.